1. Field of the Invention
The present invention generally relates to manufacture of integrated circuits and, more particularly, to methods and structures which provide improved levels of protection for electronic device structures formed on a chip while processing the chip to form other electronic device structures.
2. Description of the Prior Art
Increased density and proximity of both active and passive electronic device structures in an integrated circuit have been recognized to provide benefits in both performance and functionality of integrated circuits. For example, reduced lengths of signal propagation paths allows operation at higher clock rates while reducing susceptibility to noise. Increased numbers of devices on a single chip also generally support such improved performance while allowing a greater number and variety of circuit functions to be provided such as local voltage regulation and conversion, local memory and additional logic circuitry or co-processors for microprocessors, non-volatile storage, redundant circuitry, self-test arrangements and many other types and combinations of circuits. Even entire systems can be provided on a single chip for increasing numbers of applications. As an additional benefit of increased integration density, an increased number of different functional circuits generally tends to reduce the number of external connections which must be made to a given chip; a requirement which has presented substantial difficulty in many chip designs.
However, such increases in integration density and performance requires that individual electronic device structures be substantially optimized, at least in groups, in accordance with the functions they must perform. For example, the storage cells of a memory, collectively referred to as the array section of a memory, require very different electronic device (e.g. transistor) properties and technologies from the transistor circuits necessary to decode and address and/or carry out reading, writing and refresh operations, collectively referred to as the support section of a memory. By the same token, devices in the support section differ substantially between dynamic, static and non-volatile memory structures as well as differing substantially from devices in logic arrays, processors and the like and may operate at very different voltages and clock speeds and require much different technologies and processes to manufacture. At the same time, electronic device structures of all types are becoming more delicate with smaller process tolerance windows. Therefore, it is imperative that robust protection be provided for some regions of a chip which may include devices which may be formed or partially formed thereon while processes unnecessary for or incompatible with devices in those regions are performed to provide devices of different design or function in another region of a chip.
At the present state of the art, while many materials, such as resists, and structures for providing protection to regions of the chip, often referred to as block-out masks, are known, these materials and structures are becoming marginal in the degree of protection provided in view of the reduced size and increased criticality and delicacy of current electronic device structures while requiring increased process complexity to form suitable block-out masks. Further, at current integration densities, the registration or overlay accuracy with which block-out masks can be formed is also becoming marginal. Moreover, more sophisticated technologies and materials choices are required in current electronic device designs and selectivity of processes between those materials and the materials of block-out masks is also becoming marginal. Additionally, direct process conflicts may arise from the heat budgets, process temperatures and topographies of integrated circuit structures, the integrity of block-out masks formed thereover and the complexity of block-out mask removal (since incomplete mask removal can result in significant compromise of manufacturing yield while extended processes for resist or mask removal, generally in the nature of etching, may damage structures previously protected by the mask). In other words, the protection provided by a mask structure must not only withstand semiconductor manufacturing processes while the mask is in place but must also include a mechanism of mask removal which is highly selective to underlying semiconductor material.
The physical processes by which resists function is also a source of problems as feature sizes become smaller. Consider that a resist must absorb exposure energy or particles in order to provide selective chemical reactions when developed which result in different material solubilities such that exposed or unexposed portions of the resist may be selectively removed. Therefore, the amount of exposure energy or particle flux diminishes with depth within a layer of resist and the energy or particle flux chosen for the exposure must be sufficient to provide effective exposure through the entire thickness of the resist layer. Scattering effects also occur within the resist layer thickness and reflective effects may occur at the surface on which the resist is applied; both of which tend to broaden the exposed regions. Scattering and reflection effects increase with increasing exposure energy or particle flux. Therefore, absorption and/or scattering/reflection effects imply that thinner resist layers must be used for smaller feature size regimes even though thinner resist layers are necessarily less robust and more subject to damage or being of reduced effectiveness to protect underlying materials as well as causing increased criticality of resist removal processes.
Accordingly, so-called hard masks have been developed in which a layer of material, preferably an anti-reflective coating (ARC) and containing silicon, and more chemically stable than a developed resist is deposited by a known process such as chemical vapor deposition (CVD) and then a thin resist layer is applied and patterned to allow the pattern in the thin resist layer to be transferred to the deposited layer by, for example, a plasma etch process, allowing the patterned deposited layer to function as a somewhat more robust mask. However, such materials are difficult to remove, particularly by wet stripping processes to which they are substantially inert; severely limiting their use in manufacturing and possibly damaging surfaces they otherwise should protect due to poor selectivity between mask and underlying materials of processing reactants in order to pattern or remove the block-out or hard mask structure. Further, while the separation of imaging and pattern transfer processes, even using traditional mask materials other than ARC materials, may engender some process flexibility, additional process steps and complexity are required.
In view of the increased criticality of mask structures to the manufacture of current and foreseeable integrated circuit designs at extremely high integration densities, at least improved levels of protection of underlying structures or improved selectivity and controllability of mask removal (and preferably both) must be achieved beyond the level of performance presently available from known mask materials and selective processes in order to sufficiently protect underlying materials during both semiconductor manufacturing processes and the subsequent removal of the mask structure. As a practical matter, increased protection cannot be achieved by mere increase of mask thickness which may compromise lithographic exposures and/or chemical processes as well as mask removal.